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RF2945
11
Typical Applications
* Wireless Meter Reading * Keyless Entry Systems * 433, 868 and 915MHz ISM Band Systems * Wireless Data Transceiver * Wireless Security Systems * Battery-Powered Portable Devices
433/868/915MHZ FSK/ASK/OOK TRANSCEIVER
Product Description
The RF2945 is a monolithic integrated circuit intended for use as a low cost FM transceiver. The device is provided in 32-lead plastic LQFP packaging and is designed to be used with a PLL IC to provide a fully functional FM transceiver. The chip is intended for digital (ASK, FSK, OOK) applications in the North American 915MHz ISM band and European 433/868MHz ISM bands. The integrated VCO has a buffered output to feed the RF signal back to the PLL IC to form the frequency synthesizer. Internal decoding of the RX ENABL and TX ENABL lines allow for half duplex operation as well as turning on the VCO to give the synthesizer time to settle and complete power downmode. The DATA REF line allows the use of an external capacitor to control the DC level at the adaptive Data Slicer input for setting the bit decision threshold. Optimum Technology Matching(R) Applied
7.00 + 0.20 sq. 0.15 0.05
-A-
0.50 0.22 + 0.05 1.40 + 0.05
Dimensions in mm.
5.00 + 0.10 sq. 7 MAX 0 MIN 0.60 + 0.15 0.10
0.127
u
Package Style: LQFP-32_5x5
Si BJT Si Bi-CMOS
RX ENABL LVLADJ
GaAs HBT SiGe HBT
DATA OUT VCO OUT
GaAs MESFET Si CMOS
RESNTR+
Features
* Fully Monolithic Integrated Transceiver * 2.4V to 5.0V Supply Voltage * Narrowband and Wideband FSK * 300MHz to 1000MHz Frequency Range * 10dB Cascaded Noise Figure * 10mW Output Power With Power Control
11
TRANSCEIVERS
32
31
30
29
28
27
GND4
VCC3
VCC1
26
25
TX ENABL
1
Control Logic Gain Control
24 RESNTR-
TX OUT GND2 RX IN GND1 LNA OUT GND3 MIX IN
2 3 4 5 6 7 8
PA
23 22
MOD IN DATA REF
21 DEMOD IN 20 GND6 19 IF2 BPLinear RSSI
LNA
18 17
IF2 BP+ IF2 IN
Ordering Information
RF2945 RF2945 PCBA-L RF2945 PCBA-M RF2945 PCBA-H 433/868/915MHz FSK/ASK/OOK Transceiver Fully Assembled Evaluation Board (433MHZ) Fully Assembled Evaluation Board (868MHZ) Fully Assembled Evaluation Board (915MHz) Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com
9 GND5
10 MIX OUT+
11 VBG
12 RSSI
13 IF1 IN
14 IF1 BP+
15 IF1 BP-
16 IF1 OUT
Functional Block Diagram
RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA
Rev A10 000919
11-215
RF2945
Absolute Maximum Ratings Parameter
Supply Voltage Control Voltages Input RF Level Output Load VSWR Operating Ambient Temperature Storage Temperature
Ratings
-0.5 to +5.5 -0.5 to +5.0 +10 50:1 -40 to +85 -40 to +150
Unit
VDC VDC dBm C C Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
Parameter
Overall
RF Frequency Range
Specification Min. Typ. Max.
300 to 1000 300 to 1000 50 -20 -72 -98 2 Set by loop filter bandwidth +7 +8.5 1 +3 5 12 10 200
Unit
MHz MHz dBm dBc/Hz dBc/Hz MHz dBm dBm dB dB/V kHz Freq=433MHz Freq=915MHz
Condition
T=25 C, VCC =3.6V, Freq=915MHz
VCO and PLL Section
VCO Frequency Range VCO OUT Impedance VCO OUT Level VCO/PLL Phase Noise
Freq=915MHz 10kHz offset, 5kHz loop BW 100kHz offset, 5kHz loop BW
Transmit Section
Max Modulation Frequency Min Modulation Frequency Maximum Power Level Power Control Range Power Control Sensitivity Max FM Deviation
11
TRANSCEIVERS
Antenna Port Impedance Antenna Port VSWR Modulation Input Impedance Harmonics Spurious
50 1.5:1 4 -38
Instantaneous frequency deviation is inversely proportional with the modulation voltage. Dependent on external circuitry. TX ENABL="1", RX ENABL="0" TX Mode Freq=915MHz, with eval board filter Compliant to Part 15.249 and I-ETS 300 220
k dBc dBc MHz dB dB dB dBm dBm dBm dBm V mV/dB dB
Overall Receive Section
Frequency Range Cascaded Voltage Gain Cascaded Noise Figure Cascaded Input IP3 RX Sensitivity LO Leakage RSSI DC Output Range RSSI Sensitivity RSSI Dynamic Range -91.5 300 to 1000 35 23 10 -31 -26 -96 -55 0.5 to 2.5 22.5 80 Freq=433MHz Freq=915MHz Freq=433MHz Freq=915MHz IF BW =400kHz, Freq=915MHz, S/N=8dB Freq=915MHz RLOAD =51k
70
11-216
Rev A10 000919
RF2945
Parameter
LNA
Voltage Gain Noise Figure Input IP3 Input P1dB Antenna Port Impedance Antenna Port VSWR Output Impedance 23 16 4.8 5.5 -27 -20 -37 -30 50 1.5:1 Open Collector 8 7 10 17 -21 -17 -31 -28 0.1 10.7 34 13 330 330 10.7 60 330 1 10 25 dB dB dB dB dBm dBm dBm dBm MHz dB dB MHz dB k k MHz V dB dB dB dB dBm dBm dBm dBm 433MHz 915MHz 433MHz 915MHz 433MHz 915MHz 433MHz 915MHz RX ENABL="1", TX ENABL="0" RX Mode 433MHz and 915MHz Single-ended configuration 433MHz 915MHz 433MHz 915MHz 433MHz 915MHz 433MHz 915MHz
Specification Min. Typ. Max.
Unit
Condition
Mixer
Conversion Voltage Gain Noise Figure (SSB) Input IP3 Input P1dB
First IF Section
IF Frequency Range Voltage Gain Noise Figure IF1 Input Impedance IF1 Output Impedance IF=10.7MHz, ZL =330
Second IF Section
IF Frequency Range Voltage Gain IF2 Input Impedance IF2 Output Impedance Demod Input Impedance Data Output Bandwidth Data Output Level 0.1 25 IF=10.7MHz At IF2 OUT pin 3dB Bandwidth, ZLOAD =1M || 3pF ZLOAD =1M || 3pF. Output voltage is proportional with the instantaneous frequency deviation.
11
TRANSCEIVERS
1.4 0.3
VCC -0.3
Rev A10 000919
11-217
RF2945
Parameter
Power Down Control
Logical Controls "ON" Logical Controls "OFF" Control Input Impedance Turn On Time Turn Off Time RX to TX and TX to RX Time 2.0 1.0 25k 1 1 100 3.6 2.7 2.4 Current Consumption 17 4.8 4.4 22 6.1 6.1 3.6 27.4 7.2 6.8 1 5.0 V V ms ms s V V V mA mA mA A mA Voltage supplied to the input Voltage supplied to the input Turn on/off times are dependent upon PLL loop parameters
Specification Min. Typ. Max.
Unit
Condition
Power Supply
Voltage Specifications Operating limits Temperature range -40C to +85C Operating limits Temperature range +10C to +40C TX ENABL, LVLADJ=3.6V, RX ENABL=0V TX ENABL=3.6V, LVLADJ, RX ENABL=0V TX ENABL=0V, RX ENABL=3.6V TX ENABL, LVLADJ, RX ENABL=0V PLL Only Mode, TX ENABL, RX ENABL=3.6V, LVLADJ=0V
11
TRANSCEIVERS
11-218
Rev A10 000919
RF2945
Pin 1 Function TX ENABL Description
Enables the transmitter circuits. TX ENABL>2.0V powers up all transmitter functions. TX ENABL<1.0V turns off all transmitter functions except the PLL functions.
Interface Schematic
20 k TX ENABL 40 k
2
TX OUT
RF output pin for the transmitter electronics. TX OUT output impedance is a low impedance when the transmitter is enabled. TX OUT is a high impedance when the transmitter is disabled.
20
VCC
TX OUT
3 4
GND2 RX IN
Ground connection for the 40 dB IF limiting amplifier and Tx PA functions. Keep traces physically short and connect immediately to ground plane for best performance. RF input pin for the receiver electronics. RX IN input impedance is a low impedance when the transmitter is enabled. RX IN is a high impedance when the receiver is disabled.
500
RX IN
5 6
GND1 LNA OUT
7 8
GND3 MIX IN
Ground connection for RF receiver functions. Keep traces physically short and connect immediately to ground plane for best performance. Output pin for the receiver RF low noise amplifier. This pin is an open collector output and requires an external pull up coil to provide bias and tune the LNA output. A capacitor in series with this output can be used to match the LNA to 50 impedance image filters. Same as pin 3. RF input to the RF Mixer. An LC matching network between LNA OUT and MIX IN can be used to connect the LNA output to the RF mixer input in applications where an image filter is not needed or desired. GND5 is the ground connection shared by the input stage of the transmit power amplifier and the receiver RF mixer. IF output from the RF mixer. Interfaces directly to 10.7MHz ceramic IF filters as shown in the application schematic. A pull-up inductor and series matching capacitor should be used to present a 330 termination impedance to the ceramic filter. Alternately, an IF tank can be used to tailor the IF frequency and bandwidth to meet the needs of a given application. DC voltage reference for the IF limiting amplifiers. A 10nF capacitor from this pin to ground is required. A DC voltage proportional to the received signal strength is output from this pin. The output voltage range is 0.5V to 2.3V and increases with increasing signal strength.
VCC
LNA OUT
MIX IN GND5
9 10
GND5 MIX OUT
11
MIX OUT
15 pF GND5
15 pF GND5
11 12
VREF IF RSSI
.
VCC
RSSI
13
IF1 IN
IF input to the 40dB limiting amplifier strip. A 10nF DC blocking capacitor is required on this input.
IF1 BP+ 60 k 330 IF1 IN
IF1 BP60 k 330
Rev A10 000919
11-219
TRANSCEIVERS
RF2945
Pin 14 15 16 Function IF1 BP+ IF1 BPIF1 OUT Description
DC feedback node for the 40dB limiting amplifier strip. A 10nF bypass capacitor from this pin to ground is required. Same as pin 14. IF output from the 40dB limiting amplifier. The IF1 OUT output presents a nominal 330 output resistance and interfaces directly to 10.7MHz ceramic filters.
Interface Schematic
See pin 13. See pin 13.
IF1 OUT
17
IF2 IN
IF input to the 60dB limiting amplifier strip. A 10nF DC blocking capacitor is required on this input. The IF2 IN input presents a nominal 330 input resistance and interfaces directly to 10.7MHz ceramic filters.
IF2 IN
IF2 BP+ 60 k 330
IF2 BP60 k 330
18 19 20 21
IF2 BP+ IF2 BPGND6 DEMOD IN
DC feedback node for the 60dB limiting amplifier strip. A 10nF bypass capacitor from this pin to ground is required. Same as pin 18. Ground connection for 60dB IF limiting amplifier. Keep traces physically short and connect immediately to ground plane for best performance. This pin is the input to the FM demodulator. This pin is NOT AC coupled. Therefore, a DC blocking capacitor is required on this pin to avoid shorting the demodulator input with the LC tank. A ceramic discriminator or DC blocked LC tank resonant at the IF should be connected to this pin.
See pin 17. See pin 17.
VCC
10 k DEMOD IN
22
DATA REF
11
TRANSCEIVERS
This pin is used for setting the adaptive Data Slicer DC reference level. A capacitor from this pin to ground can be used to set the reference level at the average DC level of the data bit stream.The DC level determines the bit decision threshold.
50k
DATA REF
23
MOD IN
24
RESNTR+
FM analog or digital modulation can be imparted to the VCO through See pin 24. this pin. The VCO varies in accordance to the voltage level presented to this pin. To set the deviation to a desired level, a voltage divider referenced to Vcc is the recommended. This deviation is also dependent upon the overall capacitance of the external resonant circuit. This port is used to supply DC voltage to the VCO as well as to tune the RESNTR+ center frequency of the VCO. Equal value inductors should be connected to this pin and pin 25 although a small imbalance can be used to tune in the proper frequency range.
RESNTR-
4 k MOD IN
25 26
RESNTRVCO OUT
See RESNTR+ description. This pin is used is supply a buffered VCO output to go to the PLL chip. This pin has a DC bias and needs to be AC coupled.
See pin 24.
VCO OUT
27
GND4
GND4 is the ground shared on chip by the VCO, prescaler, and PLL electronics.
11-220
Rev A10 000919
RF2945
Pin 28 Function VCC1 Description
This pin is used to supply DC bias to the LNA, Mixer, 1st IF Amp and Bandgap reference. A RF bypass capacitor should be connected directly to this pin and returned to ground. A 22pF capacitor is recommended for 915MHz applications. A 68 pF capacitor is recommended for 433MHz applications. Demodulated data output from the demodulator. Output levels on this are TTL/CMOS compatible. The magnitude of the load impedance is intended to be 1M or greater.
Interface Schematic
29
DATA OUT
DATA OUT
30
VCC3
31
LVL ADJ
This pin is used to supply DC bias and collector current to the transmitter PA. It also supplies voltage to the 2nd IF Amplifier, Demod and data slicer. A RF bypass capacitor should be connected directly to this pin and returned to ground. A 22pF capacitor is recommended for 915MHz applications. A 68pF capacitor is recommended for 433MHz applications. This pin is used to vary the transmitter output power. An output level adjustment range greater than 12dB is provided through analog voltage control of this pin. DC current of the transmitter power amp ia also reduced with output power. NOTE: This pin MUST be low when the transmitter is disabled.
400
40 k LVL ADJ
4 k
32
RX ENABL
Enable pin for the receiver circuits. RX ENABL>2.0V powers up all receiver functions. RX ENABL<1.0V turns off all receiver functions except the PLL functions and the RF mixer.
50 k RX ENABL
Operation Mode
Sleep Mode Transmit Mode Receive Mode PLL Lock
TX ENABL RX ENABL
Low High Low High Low Low High High
Function
Entire chip is powered down. Total current consumption is <1A. * Transmitter, VCO are on. Receiver, VCO are on. * VCO is on. This mode allows time for a synthesizer loop to lock without spending current on the transmitter or receiver.
11
TRANSCEIVERS
* LVL ADJ pin must be low to disable transmitter.
Rev A10 000919
11-221
RF2945
RF2945 Theory of Operation and Application Information
The RF2945 is part of a family of low-power RF transceiver IC's that was developed for wireless data communication devices operating in the European 433MHz to 868MHz ISM band, and 915MHz U.S. ISM band. This IC has been implemented in a 15GHz silicon bipolar process technology that allows low-power transceiver operation in a variety of commercial wireless products. In its basic form, the RF2945 can be implemented as a two-way half-duplex FSK transceiver with the addition of some crystals, filters, and passive components. The RF2945 is designed to interface with common PLL IC's to form a multi-channel radio. The receiver IF section is optimized to interface with low-cost 10.7MHz ceramic filters and has a 3dB bandwidth of 25MHz and can still be used (with lower gain) at higher frequencies with other types of filters. The PA output and LNA input are available on separate pins and are designed to be connected together through a DC blocking capacitor. In the transmit mode, the PA will have a 50 impedance and the LNA will have a high impedance. In the receive mode, the LNA will have a 50 impedance and the PA will have a high impedance. This eliminates the need for a TX/RX switch, and allows for a single RF filter to be used in transmit and receive modes. Separate access to the PA and LNA allows the RF2945 to interface with external components such as a high power PA, lower NF LNA, upconverters, and downconverters, for a variety of implementations. FM/FSK SYSTEMS The MOD IN pin drives an internal varactor for modulating the VCO. This pin can be driven with a voltage level needed to generate the desired deviation. This voltage can be carried on a DC bias to select desired slope (deviation/volt) for FM systems. Or, a resistor divider network referenced to VCC or ground can divide down logic level signals to the appropriate level for a desired deviation in FSK systems. On the receiver demod, the DATA OUT pin is the output of an internal data slicer providing logic level outputs. The digital output is generated by a data slicer that compares the demodulator with a DC reference voltage recovered from the demodulator. The reference voltage is obtained by a filter capacitor on pin 22. An on-chip 1.6MHz RC filter is provided at the demodulator output to filter the undesirable 2xIF product. This type data slicer has the ability to track out minor frequency errors in the system, but requires a longer period of time for the preamble for optimum results. For 11-222 best operation of the on-chip data slicer, FM deviation needs to be larger than 40kHzP-P. The data slicer itself is a transconductance amplifier, and the DATA OUT pin is capable of driving rail-to-rail output only into a very high impedance and a small capacitance. The amount of capacitance will determine the bandwidth of DATA OUT. In a 3pF load, the bandwidth is in excess of 500kHz. The rail-to-rail output of the data slicer is also limited by the frequency deviation and bandwidth of IF filters. With the 400kHz bandwidth filters on the evaluation boards, the rail-to-rail output is limited to less than 320kHz. Choosing the right IF bandwidth and deviation versus data rate (mod index) is important in evaluating the applicability of the RF2945 for a given data rate. The primary consideration when directly modulating the VCO is the data rate versus PLL bandwidth. The PLL will track out the modulation to the extent of its bandwidth, which distorts the modulating data. Therefore, the lower frequency components of the modulating data should be five to 10 times the loop bandwidth to minimize the distortion. The lower frequency components are generated by long strings of 1's and 0's in data stream. By limiting the number of consecutive, same bits, lower frequency components can be set. In addition, the data stream should be balanced to minimize distortion. Using a coding pattern such as Manchester is highly recommended to optimize system performance. The PLL loop bandwidth is important in several system parameters. For example, switching from transmit to receive requires the VCO to retune to another frequency. The switching speed is proportional to the loop bandwidth: the higher the loop bandwidth, the faster the switching times. Phase noise of the VCO is another factor. Phase noise outside the bandwidth is because of the VCO itself, rather than a crystal reference. The design trade-offs must be made here in selecting a PLL loop bandwidth with acceptable phase noise and switching characteristics, as well as minimal distortion of the modulation data. ASK/OOK SYSTEMS The transmitter of the RF2945 has an output power level adjust (LVL ADJ) that can be used to provide approximately 18dB of power control for amplitude modulation. The RSSI output of the receiver section can be used to recover the modulation. The RSSI output is from a current source, and needs to have a resisRev A10 000919
11
TRANSCEIVERS
RF2945
tor to convert to a voltage. A 51k resistor load typically produces an output of 0.7V to 2.5V. A parallel capacitor is suggested to band limit the signal. For ASK applications, the 18dB range of the LVL ADJ does not produce enough voltage swing in the RSSI for reliable communications. The on/off keying (OOK) is suggested to provide reliable communications. To achieve this, the LVL ADJ and TX ENABL need to be controlled together (please note that LVL ADJ cannot be left high when TX ENABL is low). This will provide an on/off ratio of greater than 50dB. One of the unfortunate consequences of modulating in this manner is VCO pulling by the PA. This results in a spurious output outside the desired transmit band, as the PLL momentarily loses lock and reacquires. This may be avoided by pulse-shaping TX data to slow the change in the VCO load to a pace which the PLL can track with its given loop bandwidth. The loop bandwidth may also be increased to allow it to track faster changes brought about by load pulling. For the ASK/OOK receiver demodulator, an external data slicer is required. The RSSI output is used to provide both the filter data and a very low pass filter (relative to the data rate) DC reference to the data slicer. Because the very low pass filter has a slow time constant, a longer preamble may be required to allow for the DC reference to acquire a stable state. Here, as in the case of the FSK transmitter, the data pattern also affects the DC reference and the reliability of the receive data. Again, a coding scheme such as Manchester should be used to improve data integrity. APPLICATION AND LAYOUT CONSIDERATIONS Both the RX IN and the TX OUT have a DC bias on them. Therefore, a DC blocking cap is required. If the RF filter has DC blocking characteristics (such as a ceramic dielectric filter), then only one DC blocking cap would be needed to separate the DC of the RX and TX. These are RF signals and care should be taken to run the signal keeping them physically short. Because of the 50/high impedance nature of these two signals, they may be connected together into a single 50 device (such as a filter). An external LNA or PA may be used, if desired, but an external RX/TX switch may be required. The VCO is a very sensitive block in the system. RF signals feeding back into the VCO (either radiated or coupled by traces) may cause the PLL to become unlocked. The trace(s) for the anode of the tuning varactor should also be kept short. The layout of the resonator and varactor are very important. The capacitor and varactor should be close to the RF2945 pins, and Rev A10 000919 the trace length should be as short as possible. The inductors may be placed further away, and reducing the value of the inductors can compensate any trace inductance. Printed inductors may also be used with careful design. For best results, physical layout should be as symmetrical as possible. Figure 1 is a recommended layout pattern for the VCO components. When using the loop bandwidth lower than 5kHz shown on the evaluation board, better filtering of the VCC at the resonators (and lower VCC noise, as well) will help reduce phase noise of the VCO. A series resistor of 100 to 200, and a 1F or larger capacitor may be used.
Loop Voltage
26
25
VCC
24 23
Not to Scale Representative of Size
Figure 1. Recommended VCO Layout
For the interface between the LNA/mixer, the coupling capacitor should be as close to the RF2945 pins as possible, with the bias inductors further away. Once again, the value of the inductor may be changed to compensate for trace inductance. The output impedance of the LNA is in the order of several k, which makes matching to 50 very difficult. If image filtering is desired, a high impedance filter is recommended. The quad tank of the discriminator may be implemented with ceramic discriminator available from a couple of sources. This design works well for wideband applications where temperature range is limited. The temperature coefficient of ceramic discriminators may be in the order of +50ppm/C. The alternative to the ceramic discriminator is the LC tank, which provides a broadband discriminator more useful for high data rates.
11
TRANSCEIVERS
11-223
RF2945
PLL Synthesizer The RF2945 evaluation board uses an LMX2316 PLL IC from National Semiconductor. This PLL IC may be programmed from the software available from National Semiconductor (codeloader at www.national.com/ appinfo/wireless/). An external reference oscillator is required for the PLL IC allowing for the evaluation of different reference frequencies or step sizes. The National Semiconductor software also has a calculator for determining the R and C component values for a given loop bandwidth. The RF2945 is controlled by RX ENABL and TX ENABL which are decoded to put the RF2945 into one of four states. It may be put into a PLL-only mode with TX ENABL and RX ENABL both high. This condition is used to provide time for the synthesizer to turn on and obtain lock before turning on the receiver or transmitter. Note that LVL ADJ needs to be held low for PLLonly mode. Sometimes, it is desirable to ramp up the power amplifier to minimize load pulling on the VCO. To do this with the RF2945, first put the RF2945 into PLL mode by putting TX ENABL and RX ENABL high. Then, ramp up LVL ADJ to turn on the transmitter and PA. The rate at which LVL ADJ is allowed to ramp up is dependent on the PLL loop bandwidth. VCC pushing also affects the VCO frequency. A good low pass filter on VCC will minimize the VCC pushing effects. For applications requiring fast switching speeds or turn-on times, and low data rate loop filter bandwidths, the LMX2316 may be configured to drive the loop filter in a fast switching mode. Please refer to literature on the LMX2316 for more information.
11
TRANSCEIVERS
11-224
Rev A10 000919
RF2945
Pin Out
DATA OUT RX ENABL VCO OUT 26 RESNTR25 24 23 22 21 20 19 18 17 9 GND5 10 MIX OUT 11 VREF IF 12 RSSI 13 IF1 IN 14 IF1 BP+ 15 IF1 BP16 IF1 OUT RESNTR+ MOD IN DATA REF DEMOD IN GND6 IF2 BPIF2 BP+ IF2 IN LVL ADJ
32 TX ENABL TX OUT GND2 RX IN GND1 LNA OUT GND3 MIX IN 1 2 3 4 5 6 7 8
31
30
29
28
27
GND4
VCC3
VCC1
11
TRANSCEIVERS
Rev A10 000919
11-225
RF2945
Application Schematic - 915 MHz
VCC 10 10 nF 10 nF 10 33 pF VCC
PLL IC
10 k 4.7 nF 100 30 k 8.2 nH 330 pF TBD 10 k VCC
22 pF DATA OUT LVL ADJ RX ENABL 32 31 30
22 pF
2 pF 29 28 27 26 25 D1 SMV1233011 24
Gain Control
100
TX ENABL
1
Control Logic
8.2 nH
22 pF
10 nF
100 pF 915 MHz SAW 2 3 100 pF 4 5 10 10 nF 10 nH 6 22 pF 10 pF 8 7
PA
23 TBD 22 21 20 FM Disc. 19
Linear RSSI
MOD IN
1.5 k
VCC
LNA
10 nF
10 nF 18 10 nF 17
9
10
11
12
13 10 nF
14
15
16 10 nF Filter
VCC 8.2 uH 10 10 nF 22 pF 11 pF Filter 51 k 10 pF
RSSI
11
TRANSCEIVERS
11-226
Rev A10 000919
RF2945
Application Schematic - 915 MHz IF=25MHz, BW=2MHz
VCC2 R4 100 C81 4.7 uF C18 0.1 uF C17 22 pF VPLL R11 10 C33 0.1 uF C32 22 pF P6 DB9 VPLL/VCC2 + C29 4.7 uF + C82 4.7 uF R2 10 L3 8.2 nH C16 2 pF R1 10 C2 0.1 uF C1 22 pF L2 8.2 nH D1 SMV1233-011 C48 4.7 nF R14 10 k C50 22 pF 32 31 30 29 28 27 26 25 R13 30 k R12* 100
1
2
3
2 3
CPo
VCC2
15 14 13 12 11 10 VPLL R26 27 k R28 12 k R25 27 k R27 12 k R24 27 k R29 12 k
GND Fo/LD
C47 330 pF L7* TBD R60 0
4 5 C41 100 pF 6 7 C43 0.1 uF C34 1 nF
GND
LE
DATA OUT LVL ADJ RX ENABL
fINb Data
fIN
Clock
VPLL C44 22 pF
VCC1
CE
TX ENABL C6 22 pF L1 8.2 nH C9 4 pF R80 0 C8 4 pF
1
Control Logic Gain Control
24
8 OSCin GND 9
LMX2316
PA 2 23 22 21 20 19
Linear RSSI
50 strip
J4 MOD IN R30 51
J2 RF
50 strip C30* 4 pF C7 22 pF 3 4 5 6 C21 10 pF 7 8 C19 2.2 nF
50 strip C51* 4-22 pF L8 680 nH C20 10 nF P1 P1-1 1 2 VCC1 GND P2-1 C31 39 pF
L4 10 nH R7 10 C23 0.1 uF C22 22 pF R6* N/C
LNA
J5 REF OSC P2 1 2 3 CON3 LVL ADJ GND N/C P3-1 P3-1 P3 1 2 3 CON3 TX ENABL GND RX ENABL
18 17 C15 10 nF
C14 10 nF
9
10 C10 10 nF
11
12
13 C12 10 nF
14
15 C13 10 nF
16 C54 10 pF C53 47 pF C52 10 pF C59 47 pF L9 680 nH
L5 680 nH VCC + C5 4.7 uF R9 10 C26 0.1 uF C25 22 pF
C56 3 pF L10 680 nH
CON2
P4 P4-1 RSS I 1 2 CON2 RSSI GND P7-3 P7-1
P7 1 2 3 CON3 VCC2 GND VPLL P8-1
P8 1 2 CON2 RX OUT GND
C57 100 pF C27 39 pF C24 5 pF C55 39 pF L11 680 nH R3 51 k C11 10 pF
4
C3 0.1 uF
C4 22 pF
6
7
8
9
1
FLo
Vp
16
5
11
TRANSCEIVERS
Rev A10 000919
11-227
RF2945
Evaluation Board Schematic - 915MHz
(Download Bill of Materials from www.rfmd.com.)
VCC R2 10 C3 0.1 uF R1 10 C2 0.1 uF C1 22 pF C49 TBD J1 RX OUT P2-1 P3-3 LVL ADJ RX ENABL 32 31 30 29 28 27 26 C50 22 pF VCC R4 100 C81 4.7 uF L3 C18 0.1 uF 8.2 nH D1
SMV1233 -011
C4 22 pF R13 1.2k PLL LOOP BW ~5 kHz C42 0.1 uF R14 10 k R12 100 C47 6.8nF 1 2 3 4 5 6 7 8 FLD CPD GND GND fNb fIN Vcc1 OSCin LMX2316 Vp 16 Vcc2 15 FD/LD 14 LE 13 DATA 12 CLK 11 CE 10 GND 9 C32 22 pF C33 0.1 uF
VPLL
C41 100 pF
C17 22 pF R60 0
25
P3-2
TX ENABL C6 22 pF L1 8.2 nH C9 5 pF R80 0 C8 5 pF C30* 5 pF C7 22 pF 50 strip
1 2 3 4 5 6 7 8
Control Logic PA
Gain Control
24 23 22
C16 2 pF
L2 8.2 nH
R87* 0 R88 0
L7* TBD C58* 10 nF J4 VPLL MOD IN U4
CDF 107BA0-001 10.7 MHz
J2 RF
C19 2.2 nF C51* L8 4.7 uH
C34 1 nF
21 LNA 20 19 Linear RSSI
CAPVAR
C31 39 pF C20 10 nF
R5* 4.3 k
C43 .01 uF P6 DB9
C44 22 pF R30 51
J5 REF OSC
L4 12 nH VCC R7 10 C23 0.1 f C22 22 pF R6* N/C
C15 10 nF
6
7
8
18
1 2
9
5
R27 12 k R28 12 k R29 12 k
17
C14 10 nF F2
SFE10.7MA21
C21 10 pF 9 L5 6.8 uH VCC1 R9 10 C26 0.1 uF C25 22 pF R8 8.2 k C24 11 pF C55* 100 pF R83 0 F1 SFE10.7MA21 C57* 100 pF R84 0 C27* 10 nF L6* 2.2 uH J3 MIX OUT
2945400B
BW=400 kHz 10.7 MHz
10 C10 10nF
11
12
13
14
15
16 C13 10nF RSSI C11 10 pF
R86 0 C54* 100 pF C53* 330 pF
R85 0 C52* 100 pF
3
4
R24 27 k
R25 27 k
R26 27 k
C12 10nF R3 51 k
L10* 680 nH
R81* 560
P1 P1-1 P3 P1-3 1 P3-2 P3-3 P3-4 P3-5 2 3 4 5 GND TX ENABL RX ENABL NC NC P2-3 P2-1 P2 1 2 3 LVL ADJ GND NC P4-1 P4 1 2 RSSI GND 3 VPLL (LMX2315) 1 2 VCC (RF2945) GND
R82* 560
L11* C56* 680 nH 330 pF
C28* 120 pF * Denotes components that are normally depopulated.
11
TRANSCEIVERS
11-228
Rev A10 000919
RF2945
Evaluation Board Schematic - 433MHz
VC
C
R1 10
C2 0.1F C1 22 pF
C3 0.1F C4 22 pF
R2 VC 10 C
R 13 4.7 k P LL LO O P B W ~5 kH z C 42 33 nF C 49 220 pF VC C 50 100 pF
C
V P LL 1 R 12* 100 C 47 2.2 nF 2 3 4 F LD CPD GND GND fN b fIN V cc1 O S C in LM X 2316 V p 16 V cc2 15 F D /LD 14 LE 13 D A T A 12 C LK 11 C E 10 G ND 9 C 32 22 pF C 33 0.1 uF
J1 RX OUT P 2-1 P 3-3 LV L A D J RX ENABL 32 P 3-2 TX ENABL C6 100 pF 1 2 C7 100 pF 3 4 5 6 VC
C
R 14 20 k
R 4 100 C 81 4.7 uF L3 C 18 0.1 uF 12 nH
31
30
29
28
27
26
25
D1
S M V12 35 -0 1 1
C 17 100 pF
C 41 100pF R 60 0
5 6 7 8
C ontrol Logic PA
J2 RF
L1 22 nH C9 8 pF C8 15 pF
L9 22 nH C 30 8 pF
G ain C ontrol
24 23 22
C 16 10 pF
L2 12 nH
R 87* 0 R 88 0
L7* TBD C 58* 10 nF J4 V P LL M O D IN U4 R 5* 4.3 k
C DF 1 0 7 BA 0-0 01 1 0 .7 M Hz
C 19 2.2 nF C 51* L8 4.7 uH
C 34 1nF
21 LN A 20 19
3 -1 0 p F
C 31 39 pF C 20 10 nF
C 43 .01 uF P6 D B9
C 44 22 pF R 30 51
J5 REF OSC
L4 47 nH
C 15 10 nF
R7 10 C 23 0.1 F
R 6* N /C C 22 100 pF C 21 33 pF
7 8
Linear RSSI
6
7
8
9
5
R 27 12 k R 28 12 k R 29 12 k
18
1 2 3
17
C 14 10 nF F2
S F E 1 0 .7 M A 2 1
B W = 4 0 0 kH z 1 0 .7 M H z
9 R9 10 VC C1 C 26 0.1 uF C 25 R8 100 pF 8.2 k C 24 12 pF C 55* 100 pF R 83 0 L5 6.8 uH
10 C 10 10nF
11
12
13 14 C 12 10 nF
15
16 C 13 10 nF RSSI
R 86 0 C 54* 100 pF C 53* 330 pF
R 85 0 C 52* 100 pF
4
R 24 27 k
R 25 27 k
R 26 27 k
R3 51 k F1
S F E 1 0 .7 M A 2 1
C 11 10 pF
R 84 0 C 27* 10 nF L6* 2.2 uH J3 M IX O U T
2 94 5 4 0 1 -
L10* 680 nH
R 81* 560
P1 P 1-1 P3 P 1-3 1 P 3-2 P 3-3 P 3-4 P 3-5 2 3 4 5 G ND TX ENABL RX ENABL NC NC P 2-3 P 2-1 P2 1 2 3 LV L A D J G ND NC P 4-1 P4 1 2 RSSI G ND 3 V P LL (LM X 2315) 1 2 V C C (R F 2945) G ND
R 82* 560
L11* C 56* 680 nH 330 pF
C 57* 100 pF
C 28* 120 pF * D enotes c om ponents that are norm ally depopulated.
11
TRANSCEIVERS
Rev A10 000919
11-229
RF2945
Evaluation Board Schematic - 868MHz
VCC R2 10 C3 0.1 uF R1 10 C2 0.1 uF C1 47 pF C49* TBD J1 RX OUT P2-1 P3-3 LVL ADJ RX ENABL 32 P3-2 TX ENABL 1 2 50 strip C30* 5 pF C7 47 pF 3 4 5 6 7 8 C21 9 pF 9 L5 8.2 uH VCC1 R9 10 C26 0.1 uF C25 47 pF R8 8.2 k C24 12 pF C55* 100 pF R83 0 F1
SFE10.7MA21
C4 47 pF R13 30 k PLL LOOP BW ~5 kHz C48 4.7 nF R14 10 k R12 100 C47 330 pF 1 2 3 4 L3 C18 0.1 uF 8.2 nH D1
SMV1233 -011
VPLL
FL0 CP0 GND GND fINb fIN VCC1 OSCin LMX2316
Vp 16 VCC2 15 F0/LD 14 LE 13 DATA 12 CLK 11 CE 10 GND 9
R11 10 C32 47 pF C33 0.1 uF
VCC C50 47 pF
R4 100 C81 4.7 uF
5 C41 47 pF L7* TBD C58* 10 nF J4 VPLL MOD IN U4
CDF 107BA0-001 10.7 MHz
C17 47 pF
31
30
29
28
27
26
25
C6 47 pF L1 8.2 nH C9 5 pF R80 0 C8 5 pF
Control Logic PA
Gain Control
24 23 22
C16 3 pF
L2 8.2 nH
R60 0
6 7 8
R87* 0 R88 0
J2 RF
C19 2.2 nF C51* L8 4.7 uH
C34 1 nF
21 LNA 20 19 Linear RSSI
CAPVAR
C31 39 pF C20 10 nF
R5* 4.3 k
C43 .01 uF P6 DB9
C44 47 pF R30 51
J5 REF OSC
L4 12 nH VCC R7 10 C23 0.1 f C22 47 pF R6* N/C
C15 10 nF
6
7
8
18
1 2
9
5
R27 12 k R28 12 k R29 12 k
17
C14 10 nF F2
SFE10.7MA21
BW=400 kHz 10.7 MHz
10 11 C10 10 nF
12
13 14 C12 10 nF
15
16 C13 10 nF RSSI
R86 0 C54* 100 pF C53* 330 pF
R85 0 C52* 100 pF
3
4
R24 27 k
R25 27 k
R26 27 k
R84 0
R3 51 k
C11 10 pF
L10* 680 nH
R81* 560
P1 P1-1 P3 P1-3 1 P3-2 P3-3 P3-4 P3-5 2 3 4 5 GND TX ENABL RX ENABL NC NC P2-3 P2-1 P2 1 2 3 LVL ADJ GND NC P4-1 P4 1 2 RSSI GND 3 VPLL (LMX2315) 1 2 VCC (RF2945) GND
R82* 560
L11* C56* 680 nH 330 pF
C57* 100 pF
C27* 10 nF L6* 2.2 uH J3 MIX OUT
2945402-
C28* 120 pF * Denotes components that are normally depopulated.
11
TRANSCEIVERS
11-230
Rev A10 000919
RF2945
Evaluation Board Layout - 915MHz Board Size 3.050" x 3.050"
Board Thickness 0.031", Board Material FR-4
11
TRANSCEIVERS
Rev A10 000919
11-231
RF2945
11
TRANSCEIVERS
11-232
Rev A10 000919
RF2945
Evaluation Board Layout - 433MHz
11
TRANSCEIVERS
Rev A10 000919
11-233
RF2945
11
TRANSCEIVERS
11-234
Rev A10 000919
RF2945
Evaluation Board Layout - 868MHz
11
TRANSCEIVERS
Rev A10 000919
11-235
RF2945
11
TRANSCEIVERS
11-236
Rev A10 000919
RF2945
2.5
RSSI Output versus Temperature VCC = 2.4 V, 915 MHz
-40C 10C 25C 40C 85C
10.0
POUT versus Level Control and VCC 915 MHz and Temperature = 25C
2.0
0.0
RSSI Output (V)
POUT (dBm)
1.5
-10.0
1.0
-20.0 0.5
Vcc=2.4V Vcc=2.7V Vcc=3.0V Vcc=3.3V Vcc=3.6V Vcc=3.9V Vcc=4.2V Vcc=4.5V Vcc=4.8V 0.0 1.0 2.0 3.0 4.0 5.0
0.0 -130.0
-30.0 -110.0 -90.0 -70.0 -50.0 -30.0 -10.0 10.0
Received Signal Strength (dBm)
Level Control (V)
10.0
TX Power Output and ICC versus Level Adjust at 433MHz, 3.6V VCC
Pout(433) Icc(433)
30.0
5.0
TX Power Output and ICC versus Level Adjust at 868MHz, 3.6V VCC
Pout(868) Icc(868)
30.0
5.0
25.0
0.0
25.0
RF P0 (dBm)
ICC (mA)
-5.0
15.0
-10.0
15.0
ICC (mA)
0.0
20.0
RF P0 (dBm)
-5.0
20.0
-10.0
10.0
-15.0
10.0
11
TRANSCEIVERS
-15.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
5.0
-20.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
5.0
LVL ADJ (V)
LVL ADJ (V)
5.0
TX Power Output and ICC versus Level Adjust at 905MHz, 3.6V VCC
Pout(905) Icc(905)
30.0
9.0 Icc (433) Icc (868) Icc (905)
Receive Current versus VCC (Excluding PLL IC)
0.0
25.0
8.0
RF P0 (dBm)
ICC (mA)
-10.0
15.0
ICC (mA)
-5.0
20.0
7.0
6.0
-15.0
10.0
5.0
-20.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
5.0
4.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
LVL ADJ (V)
Supply Voltage (V)
Rev A10 000919
11-237
RF2945
11
TRANSCEIVERS
11-238
Rev A10 000919

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